More details emerge on the Intel/TSMC deal and Moorestown
July 6, 2009
A new rumor in the Chinese-language Commercial Times, picked up by DigiTimes, indicates that Intel will use some intellectual property from its new foundry partner, TSMC, to fill out its upcoming ultramobile chipset, codenamed Langwell. This rumor, which I suspect is true, may provide the answers to long-standing questions about two different aspects of Intel’s plans for Atom and its derivatives. But, before we get to the questions, let’s talk about Langwell.
Langwell is the southbridge (or I/O hub) for Intel’s forthcoming Atom successor, codenamed Moorestown. Above is a block diagram of Moorestown that shows the platform’s two main components: the SoC, codenamed Lincroft, and the I/O hub, codenamed Langwell.
As you can see from the diagram, Lincroft features an Atom-derived CPU core, a GPU core, a memory controller, and two video processing blocks. Langwell features a solid state disk controller, a system controller, and an unspecified number of I/O blocks of indeterminate makeup. This latter part is where the DigiTimes rumor comes in.
Chronologically speaking, the first question that the new rumor sheds light on is about the mysterious I/O blocks, which have not been identified even as more recent Moorestown features have been revealed. With the news that Intel will fab Langwell on TSMC’s process and customize the chip using non-Intel IP blocks, we now know that these "I/O blocks" are left unspecified by design. As in, a hypothetical fab customer who wants a customized version of Langwell will specify the number and nature of the (TSMC-authored) IP blocks that go into the empty slots.
The other interesting thing about this rumor is that it gives insight into how Intel will use its relationship with TSMC. Intel has maintained from the start that their intention is to offer potential "embedded x86" customers more options for using its processor designs for different applications, with customization being essential to these plans. My reading of this was that they would be let customers use third-party IP on the SoC part of the chipset, but clearly the real target for customization is the I/O hub.
Focusing all of the customization on the I/O hub makes total sense, both because it’s the least complex of the two, and also because customer I/O requirements are what vary most by planned application. There’s no point in buying chipset where the I/O hub supports six USB ports if your hardware doesn’t need USB. On the flip side, the embedded world may feature a plethora of domain-specific or even proprietary interfaces that individual volume customers need support for (I’m just guessing here, though, because I don’t know the larger embedded space super well). Either way, confining the customization to the 65nm I/O hub will maximize the strategy’s effectiveness while minimizing its impact on development and fab costs.
This post has been written by Jon Stokes on July 5, 2009 8:30 PM couresy of arstechnica.com.